Huawei Announces 'Tau Scaling Law' and LogicFolding Architecture — Projects 1.4nm-Equivalent Chips by 2031 Without TSMC

At the 2026 IEEE ISCAS (International Symposium on Circuits and Systems) conference in Shanghai on May 25, 2026, Huawei Technologies CEO He Tingbo unveiled the Tau (τ) Scaling Law — a new semiconductor scaling paradigm to replace geometric transistor shrinkage (Moore's Law). Rather than shrinking physical transistor size, Tau scaling compresses signal propagation delay (the τ constant) through the 'LogicFolding' chip architecture, which vertically stacks functional layers to reduce interconnect distances. Huawei projects the first Kirin chips using LogicFolding for Fall 2026, with a roadmap to 1.4nm-equivalent logic density by 2031 using domestic SMIC foundry processes — without requiring ASML extreme ultraviolet (EUV) lithography machines banned under US/Dutch export controls. Fortune described Huawei as 'touting a chip breakthrough to shorten the gap with TSMC.' The announcement comes amid Nvidia CEO Jensen Huang separately acknowledging on May 21 that Nvidia has 'largely conceded' China's $67B AI chip market to Huawei due to US export restrictions.